This invention relates to a process for manufacturing integrated circuits which include non-volatile memory cells and peripheral transistors.
Most up-to-date applications of integrated circuits concern systems which are supplied voltages in the 3-volt range. Such systems often utilize semiconductor storage facilities of the non-volatile type. In order to retain the characteristics of these devices at low supply voltages, it has been necessary to employ thin oxides (160 xc3x85-thick or less). However, it is well recognized that memories of the EPROM, EEPROM, FLASH types require high programming voltages (12V) which cannot be accommodated by such thin oxides. Accordingly, the requirement involves the concurrent provision of thick and thin oxides in one device, which burdens the process technology with at least one additional masking operation.
As for the peripheral transistors, these are incorporated in circuits outside the array of memory cells, such as array control logics or circuits, and are frequently expected to withstand high voltages, on the order of 12 to 15 volts. In describing this invention, reference will be made specifically to transistors of the MOS type.
Such transistors include an active dielectric, or gate dielectric, placed between the substrate and a gate made of an electrically conductive material, usually polysilicon. In general, the active dielectric consists of a layer of silicon oxide obtained by oxidation of the substrate at a high temperature.
Processes for manufacturing integrated structures which include non-volatile memory cells, i.e. cell matrices set up into rows and columns, using dual levels of polysilicon with a gate dielectric layer and an isolating interpoly dielectric layer therebetween, have been known and extensively used in the industry.
Such manufacturing processes may provide for a first masking and implanting step effective to define well regions having conductivity of a different type from that of the semiconductor substrate, in order to provide N-channel and P-channel devices on one chip. Conventional processes essentially utilize, therefore, one mask to define the active areas of the individual integrated devices (transistors, floating-gate memory cells, etc.). The process normally provides for an additional masking step, in order to form field isolation implants, that is, to have the semiconductor implanted in those zones where a thick oxide layer will be later grown to define and isolate the individual active areas.
The process may provide for an ATP (Anti-Punch Through) implantation of all those active areas that have the same type of conductivity. A relatively heavy threshold-raising implantation (EPM) is performed in the matrix area where the floating-gate memory cells are to be formed. A thin layer of gate oxide is then grown over the active areas. Subsequent to the depositing and doping of a first-level polysilicon layer (poly 1), a masking and etching step is usually carried out for a first definition of the first-level polysilicon that is to provide the floating gates for the memory cells.
A thin dielectric layer is next grown and/or deposited over the entire structure to isolate the two polysilicon levels (interpoly). This thin dielectric isolation layer may be a multiple layer, typically comprised of a first oxidation. layer, a thin second layer of deposited silicon nitride, and a third nitride oxidation layer (the so-called O.N.O. multi-layer). At this stage, a masking step is typically carried out in such processes using a mask commonly referred to as the xe2x80x9cmatrix maskxe2x80x9d, thereby to remove the interpoly dielectric isolation layer from all over the surface except the area being occupied by the memory cells (matrix). Thereafter, a second-level doped polysilicon layer is deposited which, in the formation area of the floating-gate memory cells, will thus be isolated from the interpoly dielectric layer by the first-level polysilicon portions previously defined. On the other hand, the second layer of doped polysilicon will directly overlie the existing first-level layer of polysilicon, in areas outside the area being occupied by the memory cell matrix, that is the areas where the transistors and other external circuit devices are formed.
Conventional processes may also require a masking step specifically to perform an implantation, known as the LVS (Light Voltage Shift) implant, for slightly adjusting the threshold of standard enhancement transistors in the circuitry, with the channel areas of the so-called xe2x80x9cnaturalxe2x80x9d (or low threshold) transistors screened off the LVS implant. By an additional masking (poly 2) and etching step, the second-level polysilicon is defined which, in the matrix area, is terminated at the interpoly dielectric layer and, in the circuit area, also results in the underlying first-level polysilicon being defined, thereby defining the channel length of the transistors in the circuit.
A manufacturing process as described above is disclosed in prior Italian Patent Application No. 23737-A/84 and, inter alia, the corresponding patent publication GB-2,167,602, both in the name of this Applicant. It is intended that the contents of these prior publications be incorporated herein by reference, wherever appropriate.
What is needed is a process for forming non-volatile memory cells and thick-oxide peripheral transistors by a minimum number of steps, and accordingly, for lower production costs.
Accordingly, the present invention provides a process for manufacturing a thick-oxide transistor having an active area region in an integrated circuit which which also includes a matrix area of floating-gate non-volatile memory cells having dual polysilicon levels isolated from each other by a gate dielectric layer and an interpoly dielectric layer therebetween. The process comprises an optional step for defining well regions. The process further comprises at least one masking step for defining the active areas of individual integrated devices, a masking step for defining an implant in the matrix area, a masking step for defining a first-level polysilicon to form floating-gate structures for the memory cells within the matrix area, a matrix masking step for etching away said interpoly dielectric layer from areas outside the matrix area, at least one masking step for defining a second-level polysilicon, and wherein the masking step for defining the first-level polysilicon includes removal of the polysilicon from the active area region of the thick-oxide transistor.
The present invention also provides an integrated circuit on a semiconductor material substrate. The integrated circuit comprises at least one matrix of non-volatile memory cells, wherein each cell has an electrically conductive floating gate, formed by a masking operation f or defining a first-level polysilicon layer, which is isolated electrically between a first dielectric layer of silicon oxide and a second dielectric layer including at least one layer of silicon oxide; and further comprising in regions peripheral to the matrix, at least a first type of transistors including an active area region having a thick gate oxide, wherein said thick gate oxide of said transistors comprises said first and second dielectric layers.